In certain CCD applications it is desirable to be able to time-division multiplex several hundreds of samples supplied parallelly in time, so as to rearrange them to be serial in time. An application for such a parallel-to-serial converter that is of particular interest to the inventor is involved with the provision of line array short-wave infrared detectors for satellite cameras of the push-broom type. These line arrays are required to have resolution in the direction of line scan that involves thousands of image elements, or pixels. Infrared sensing per se is done in diode structures using platinum silicide Schottky barrier contacts to p-type silicon, with each sensor diode structure being about thirty microns square. U.S. Pat. No. 4,467,342, issued 21 Aug. 1984, to J. R. Tower and entitled "MULTI-CHIP IMAGER" teaches how to make such an ultra-long line array of large sensor diode structures, by using a plurality of semiconductor dies having disposed on them respective component line arrays of a few hundred charge transfer stages length. The dies are abutted to form the full length of the ultra-long line array of large sensor diode structures.
The use of buttable component linear arrays reduces the problem of parallel-to-serial conversion of several thousand samples to the problem of replicated parallel-to-serial conversions, each of several hundred samples. But it introduces the limitation that side-loaded CCD registers used for parallel-to-serial conversion must not extend beyond the linear arrays of photosensors they share the same semiconductor die with. This limitation can be accommodated by incorporating parallel transfer registers for connecting the photosensors to the CCD shift register they side-load, which parallel transfer registers use fan-in to cause their parallelly arrayed output ports to be narrower than their parallelly arrayed input ports.
A problem is encountered with dividing the full linear array into component linear arrays located in separate buttable semiconductor dies, such that component linear arrays are short enough to be parallel-to-serial converted without encountering transfer efficiency problems. At the 77 to 125K temperature at which the linear arrays are operated, the limitation on the number of successive charge transfers in the side-loaded CCD shift register before transfer efficiency problems become significant is around five hundred or so, for the clock-out interval contemplated (four milliseconds). If one uses a two-phase side-loaded CCD shift register for parallel-to-serial conversion, this limits shift register length to two-hundred-fifty or so stages. Limiting die width to fit one CCD shift register of such length across most of that width results in a die that is too small by present-day layout rules to accommodate a desired number of bond pads for input/output connections. So two CCD shift registers in linear alignment are to be fitted across the die width. Fitting more than two CCD shift registers in line across the length of a semiconductor die results in a die that is too large to be manufactured with acceptably high yield using present-day technology, as well as unduly increasing the number of electrometers, buffer amplifiers and bond pads on the die.
There is a problem with matching the charge-to-voltage conversion characteristics of electrometers. Some adjustments to accommodate differences in these conversion characteristics invariably must be made. Consequently, it is desirable to share the same electrometer for the two CCD shift registers in line across the width of the same semiconductor die. In order to continue to avoid the problems of transfer inefficiency caused by too many successive charge transfers, it is desirable to avoid substantial additional charge transfers in connecting the CCD shift registers to the shared electrometer.
The use of two CCD shift registers in linear alignment both connecting to a shared electrometer stage is also of interest in visible-light CCD imagers. While such imagers are normally operated around 300K, which higher temperature improves transfer efficiency, the CCD shift registers used for parallel-to-serial conversion are normally operated at a several MHz clock rate, which hampers efficient charge transfer.